The present invention relates to the field of integrated circuits and more particularly to interconnections of integrated circuit devices and related methods and structures.
High performance microelectronic devices often use solder balls or solder bumps for electrical interconnection to other microelectronic devices. For example, a very large scale integration (VLSI) chip may be electrically connected to a circuit board or other next level packaging substrate using solder balls or solder bumps. This connection technology is also referred to as xe2x80x9cControlled Collapse Chip Connectionxe2x80x94C4xe2x80x9d or xe2x80x9cflip-chipxe2x80x9d technology, and will be referred to herein as solder bumps.
According to solder bump technology developed by IBM, solder bumps are formed by evaporation through openings in a shadow mask which is clamped to an integrated circuit wafer. For example, U.S. Pat. No. 5,234,149 entitled xe2x80x9cDebondable Metallic Bonding Methodxe2x80x9d to Katz et al. discloses an electronic device with chip wiring terminals and metallization layers. The wiring terminals are typically essentially aluminum, and the metallization layers may include a titanium or chromium localized adhesive layer, a co-deposited localized chromium copper layer, a localized wettable copper layer, and a localized gold or tin capping layer. An evaporated localized lead-tin solder layer is located on the capping layer.
Solder bump technology based on an electroplating method has also been actively pursued. The electroplating method is particularly useful for larger substrates and smaller bumps. In this method, an xe2x80x9cunder bump metallurgyxe2x80x9d (UBM) layer is deposited on a microelectronic substrate having contact pads thereon, typically by evaporation or sputtering. A continuous under bump metallurgy layer is typically provided on the pads and on the substrate between the pads, in order to allow current flow during solder plating.
An example of an electroplating method with an under bump metallurgy layer is discussed in U.S. Pat. No. 5,162,257 entitled xe2x80x9cSolder Bump Fabrication Methodxe2x80x9d to Yung and assigned to the assignee of the present application. In this patent, the under bump metallurgy layer includes a chromium layer adjacent the substrate and pads, a top copper layer which acts as a solderable metal, and a phased chromium/copper layer between the chromium and copper layers. The base of the solder bump is preserved by converting the under bump metallurgy layer between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under bump metallurgy layer.
According to aspects of the present invention, metallurgy structures can be provided for input/output pads of an electronic device comprising a substrate, and first and second input/output pads on the substrate. In particular, first and second metallurgy structures can be provided on the respective first and second input/output pads, with the first and second metallurgy structures having a shared metallurgy structure adapted to receive solder and wire bonds. The metallurgy structures can thus be formed efficiently at the same time to facilitate solder bonding to another substrate and wire bonding to a next level packaging structure.
According to additional aspects of the present invention, metallurgy structures according to the present invention can include an underbump metallurgy layer on an input/output pad, a barrier layer on the underbump metallurgy layer, and a passivation layer on the barrier layer. Such a structure can accept either a wire bond or a solder bond.
According to further aspects of the present invention, an electronic device can include a substrate, an input/output pad on the substrate, and a bonding structure on the input/output pad. More particularly, the bonding structure can include a barrier layer comprising nickel on the input/output pad, and a solder structure on the barrier layer.
According to yet further aspects of the present invention, first and second barrier layers can be provided on the respective first and second input/output pads wherein the first and second barrier layers each comprise nickel. First and second passivation layers can be provided on the respective first and second barrier layers, and a solder structure can be provided on the first passivation layer while maintaining the second passivation layer free of solder.